Resistive memory cells and devices having asymmetrical contacts

ABSTRACT

A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is continuation of U.S. patent application Ser.No. 12/612,187, filed Nov. 4, 2009, which is a Divisional Application ofU.S. patent application Ser. No. 11/378,945, filed Mar. 17, 2006 in theUnited States Patent Office which claims the benefit of Korean PatentApplication No. 2005-25561, filed Mar. 28, 2005, the disclosures ofwhich are hereby incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to memory devices and, more particularly,to magneto-resistive memory devices and methods of fabricating the same.

A resistive memory cell is a nonvolatile memory cell containing aresistive memory element that can reversibly switch between twodifferent resistance states responsive to applied voltage. Colossalmagneto-resistive material (CMR) is widely used as a resistive memoryelement. A resistive memory cell using a CMR element is disclosed inU.S. Pat. No. 6,849,891. The resistive memory cell disclosed in the U.S.Pat. No. 6,849,891 is illustrated in FIG. 1.

Referring to FIG. 1, a conventional magneto-resistive memory cell 18includes a CMR layer 24, a bottom electrode 20, 22 contacting to abottom of the CMR layer 24, and a top electrode 26, 28 contacting a topof the CMR layer 24. The bottom electrode and the top electrode may havethe same structure and are formed of an oxidation resistance layer 20,28 and a refractory metal layer 22, 26. The magneto-resistive memorycell 18 is formed by depositing layers 20, 22, 24, 26 and 28 andpatterning the deposited layers 20, 22, 24, 26 and 28 usingphotolithography.

A desirable characteristic for such a cell is a switching operationcharacteristic that allows clear discrimination between two reversibleswitching states. The resistive memory cell can provide a reliablememory function when it has two resistance states that may be clearlydiscriminated from a reference value. If the two resistance states areambiguous, the resistive memory cell may not function well as a memorycell.

In addition, it is desirable for the resistive memory cell to maintaingood switching characteristics after repeated memory operations, i.e.,it is desirable that the resistive memory cell maintain a certain valueof a low resistance state and a certain value of a high resistance stateeven after repeated operation. This is related to an endurance of thememory cell.

The structure of the conventional magneto-resistive memory cell 18 shownin FIG. 1 may not provide a good switching operation characteristic.Because the bottom electrode 22, the CMR layer 24 and the top electrode26 are simultaneously formed, an overlapping area between the CMR layer24 and the bottom electrode 22 is the same as the area of the CMR layer24. Accordingly, when a voltage is applied to the two electrodes 22 and26, the entire CMR layer 24 becomes a switching region in whichresistance variation occurs. Because the entire CMR layer 24 serves asthe switching region, the position/size/number of filamentary currentpaths that are switched on and off may not be constant, such thatresistance states may not be constant. Consequently, the low resistancestate and the high resistance state may be ambiguous.

In addition, it is known that heat resistant metal, which may be usedfor the bottom electrode 22, may be difficult to etch. For this reason,a side profile of the bottom electrode 22 may be inclined rather thanvertical. Accordingly, it may be necessary to increase distance betweenneighboring resistive memory cells to prevent neighboring cells fromelectrically shorting. However, this increased distance betweenneighboring memory cells may serve as an obstacle to the implementationof a highly integrated memory device.

SUMMARY OF THE INVENTION

In some embodiments of the present invention, a memory cell includes aplug-type first electrode in a substrate, a magneto-resistive memoryelement disposed on the first electrode, and a second electrode disposedon the magneto-resistive memory element opposite the first electrode.The second electrode has an area of overlap with the magneto-resistivememory element that is greater than an area of overlap of the firstelectrode and the magneto-resistive memory element. The area of overlapof the first electrode may, for example, be substantially circular andhave a diameter less than a minimum planar dimension (e.g., width) ofthe area of overlap of the second electrode. The magneto-resistivememory element may include a colossal magneto-resistive material, suchas an insulating material with a perovskite phase and/or a transitionmetal oxide.

In some embodiments, the first electrode is disposed in an insulatinglayer and an insulating spacer is disposed between the first electrodeand the insulating layer. The first electrode may partially fill acontact hole in the insulating layer, and the magneto-resistive memoryelement may extend into the contact hole to contact the first electrode.

In additional embodiments of the present invention, a memory deviceincludes a plurality of first electrode lines arranged in parallel on asubstrate. A plurality of second electrode lines is arranged in parallelon the substrate transverse to the first electrode lines. A plurality ofelectrode plugs is electrically coupled to the first electrode lines.Respective ones of the electrode plugs are disposed between ones of thefirst and second electrode lines at respective intersections thereof.The device further includes a plurality of magneto-resistive memoryelements, a respective one of which has a first surface electricallycoupled to a respective one of the electrode plugs and a second surfaceelectrically coupled to a second electrode line, wherein the secondsurface has a greater area than the first surface.

The plurality of magneto-resistive memory elements may include an arrayof individual patterns disposed between ones of the first and secondelectrode lines at respective intersections thereof. In someembodiments, the plurality of magneto-resistive memory elements mayinclude a plurality of regions in a magneto-resistive material layerthat overlaps multiple ones of the electrode plugs.

In yet further embodiments of the present invention, a memory deviceincludes respective pluralities of parallel electrode lines disposed ona substrate at respective levels, wherein pluralities of electrode lineson adjacent levels extend transverse to one another. The device furtherincludes respective insulating layers between the pluralities ofelectrode lines of adjacent levels. Respective pluralities ofmagneto-resistive memory elements are disposed between adjacent ones ofthe insulating layers and the pluralities of electrode lines. Respectivepluralities of electrode plugs penetrate respective ones of theinsulating layers at intersections of the electrode lines and couple theelectrode lines to the magneto-resistive memory elements. The electrodeplugs may have a diameter smaller than a width of the electrode lines.The magneto-resistive memory elements may include layer patterns havingsubstantially the same shape as the electrode lines.

Further embodiments of the present invention provide methods offabricating a memory cell. An insulating layer is formed on a substrate,and a contact hole is formed in the insulating layer. A first electrodeis formed in the contact hole, and a magneto-resistive memory element isformed on the first electrode. A second electrode is formed on themagneto-resistive memory element. An area of overlap of themagneto-resistive memory element and the first electrode may be lessthan an area of overlap of the magneto-resistive memory element and thesecond electrode. The magneto-resistive memory element may be patternedsimultaneously with the second electrode. In some embodiments, prior tothe forming of the first electrode plug, insulating spacers may beformed on sidewalls of the first contact hole. A second insulating layermay be formed on the second electrode and patterned to form a secondcontact hole exposing a portion of the second electrode. A thirdelectrode may be formed in the second contact hole, and a secondmagneto-resistive memory element may be formed on the third electrode. Afourth electrode may be formed on the second magneto-resistive memoryelement.

Some embodiments of the present invention may provide resistive memorycells capable of reducing an overlapping area or contact area between aresistive memory element thin film and an electrode. A resistive memorycell may include a resistive memory element thin film and two electrodes(first electrode and second electrode) connected to both sides of theresistive memory element thin film. One (e.g., the first electrode) ofthe two electrodes may be configured to be a plug (e.g., first electrodeplug) so as to reduce the contact area between the electrode and theresistive memory element thin film, For example, the first electrode maybe defined within a contact hole formed in an insulating layer. Thefirst electrode plug can be easily formed using general semiconductorfabricating processes, such as a contact hole process, a conductivematerial depositing process, an a planarization process.

The overlapping area or contact area between the first electrode plugand the resistive memory element thin film may depend on a diameter ofthe first electrode plug. In some embodiments, a diameter of theelectrode plug is smaller than a minimum width of a bottom electrode ofthe conventional resistive memory cell of FIG. 1. In addition, aninsulating spacer may be further formed within the contact hole afterthe contact hole process in order to further reduce the diameter of thefirst electrode plug.

A resistive memory cell according to some embodiments of the presentinvention may exhibit good switching operation characteristic becausethe overlapping area between the electrode and the resistive memoryelement thin film is reduced. In addition, unlike the prior art as shownin FIG. 1, the first electrode plug may be restricted within the contacthole. Therefore, because photolithography for the first electrode maynot be required, it may be advantageous to the implementation of highlyintegrated memory devices.

When a first electrode is defined within the contact hole, the firstelectrode can fill an entire contact hole or a portion of the contacthole. In the latter case, a portion of the resistive memory element thinfilm can be positioned within the contact hole. That is, the firstelectrode can fill a portion of the contact hole and the resistivememory element can fill a remaining portion of the contact hole.

The resistive memory element thin film may include a material that canreversibly switch between at least two resistance states, which aredistinctly discriminated by a predetermined voltage applied to both endsof the resistive memory element thin film. For example, the resistivememory element thin film may be formed of material selected from thegroup consisting of an insulating material with perovskite phase,insulating metal oxide MO_(x), or a combination thereof. The insulatingmaterial with perovskite phase may be an insulating material having aso-called ABO₃ structure. Examples of the insulating material withperovskite phase include, but at not limited to, PbZrTiO₃, PrCaMnO₃,calcium-doped (Ba, Sr)TiO₃, SrZrO₃, and so on, but are not limited tothem. An insulating metal oxide (MO_(x)) may be transition metal oxideor noble metal oxide. Examples of the transition metals include, but arenot limited to, nickel (Ni), niobium (Nb), titanium (Ti), zirconium(Zr), hafnium (Hf), cobalt (Co), iron (Fe), copper (Cu), manganese (Mn),and chromium (Cr). A transition metal oxide can also contain impurities,such as lithium, calcium, and lanthanum. The first and second electrodesmay be formed from, for example, iridium, platinum, ruthenium,polycrystalline silicon, tungsten (W), titanium nitride (TiN), titaniumaluminum nitride (TiAlN), or a combination thereof.

In a resistive memory cell according to some embodiments of the presentinvention, the resistive memory element thin film reversibly switchesbetween the low resistance state and the high resistance state by thevoltage that is appropriately applied to the first electrode and thesecond electrode. Defects of the resistive memory element thin film maygenerate impurity states in an energy band gap. Depending on thepresence or absence of the impurity states, the resistive memory elementthin film may exhibit two distinguishable resistance states. Due to theimpurity states, a filamentary current path of a low resistance may beformed, or a filamentary current path already formed may disappear,depending on the applied voltage. For example, metal or oxygen vacanciesmay generate density of states near the valance or conduction bandrespectively, while metal defects may do the same just above theelectrode Fermi level.

When a metallic defect state is generated above the Fermi level of theresistive memory element thin film, the resistive memory cell may takeon a low resistance state (e.g., a set state). On the contrary, when themetallic defect state disappears, the resistive memory cell may take ona high resistance state (e.g., a reset state). For a switching betweenthe set state and the reset state, different voltages may be applied totwo electrodes of the resistive memory cell. A reset voltage for thereset state may be lower than a set voltage for the set state. Forexample, the set voltage may be 1.5-2.5 times the reset voltage.

In order to make a resistive memory element thin film transition to theset state, a first voltage can be applied for about 1-100 ns, preferablyabout 1-10 ns. Meanwhile, in order to make a resistive memory elementthin film transition to the reset state, a second voltage can be appliedfor about 1-100 μs, preferably about 1-10 μs. Under the condition thatthe set voltage is higher than the reset voltage, the set voltage may be0.15-7.5 V and the reset voltage may be 0.1-3 V. In some embodiments,the set voltage may be 1-2 V and the reset voltage may be 0.4-0.8 V. Theset voltage and the reset voltage may depend on thickness of theresistive memory element thin film.

Assuming that a reset current is a current flow when changing from theset state to the reset state, and a set current is a current flow whenchanging from the reset state to the set state, the reset current may begreater than the set current. Accordingly, by applying an appropriatevoltage or current regardless of polarity, the resistive memory cell maybe programmed to the set state or the reset state, regardless of theprevious states of the resistive memory cell. In order to read the datafrom the resistive memory cell, a voltage at which the resistive memorycell is not reset, that is, a voltage lower than the reset voltage, maybe applied.

An initial set voltage just after the resistive memory element thin filmis initially formed, that is, a forming voltage, is somewhat associatedwith thickness of the resistive memory element thin film formed of thetransition metal oxide. As the resistive memory element thin film isthinner, the forming voltage may be decreased. Accordingly, it may bedesirable that the resistive memory element thin film be thinner for lowvoltage operation.

The set voltage and the reset voltage may be influenced by oxygencontent of a resistive memory element thin film formed of the transitionmetal oxide. Accordingly, it may be desirable that a resistive memoryelement formed of the transition metal oxide have a certain oxygencontent.

For a resistive memory cell operating at the low voltage or current, thecomposition of the transition metal oxide may be controlled. It may bedesirable that oxygen composition ratio of the transition metal oxide issmaller than oxygen composition ratio of the stable state. In otherwords, it may be desirable that the transition metal oxide has arelatively large transition metal content compared with its stablestate. For example, in transition metal oxide expressed as MO_(x), whenthe metal “M” is nickel (Ni), cobalt (Co), Zinc (Zn), or copper (Cu),“x” representing the composition ratio of oxygen atoms has the rangefrom 0.5 to 0.99 (0.5≦x≦0.99). On the contrary, when the metal “M” ishafnium (Hf), zirconium (Zr), titanium (Ti), or chromium (Cr), “x”representing the composition ratio of oxygen atoms has the range from1.0 to 1.98 (1.0≦x≦1.98). When the metal “M” is iron (Fe), “x”representing the composition ratio of oxygen atoms has the range from0.75 to 1.485. Also, when the metal “M” is niobium (Nb), “x”representing the composition ratio of oxygen atoms has the range from1.25 to 2.475.

Using various techniques, a transition metal oxide can be formed to havethe above composition ratio of oxygen atoms. For example, the transitionmetal oxide can be formed by alternately and repeatedly performing anoperation of forming a transition metal layer and an operation ofoxidizing the transition metal layer using an oxygen plasma treatment.The transition metal layer can be formed using a sputtering technique.Also, the oxygen plasma treatment can be performed in-situ. In someembodiments, the transition metal oxide layer can be formed using O₂reactive sputtering technique, a chemical vapor deposition (CVD)technique, or an atomic layer deposition (ALD) technique.

Some embodiments of the present invention provide methods of fabricatinga resistive memory cell capable of reducing the overlapping area betweenthe resistive memory element thin film and the electrode. In someembodiments, a first electrode plug is formed within an insulatinglayer, and a resistive memory element thin film and a conductive layerfor a second electrode is formed. The forming of the first electrodeplug may include patterning the insulating layer to form a contact hole,and filling the contact hole with a conductive material. The filling ofthe contact hole with the conductive material can be achieved bydepositing and planarizing the conductive material. Examples of theplanarization process are a chemical mechanical polishing (CMP) and anetch-back process.

The resistive memory element thin film need not be separated betweenadjacent cells. For electrical separation of the second electrodebetween adjacent cells, a conductive layer for the second electrode maybe patterned by photolithography. Unlike the prior art as shown in FIG.1, the first electrode plug acting as the bottom electrode need notundergo photolithography, so that thickness of the patterned layer maybe less than that of the prior art as shown in FIG. 1. Consequently,highly integrated resistive memory devices can be implemented.

Some embodiments of the present invention provide resistive memoryarrays. The resistive memory array may include: a plurality of firstelectrode lines arranged in parallel from one another; a plurality ofsecond electrode lines intersecting the first electrode lines andarranged in parallel from one another; a plurality of resistive memoryelement patterns positioned on a first surface of the first electrodelines or a second surface of the second electrode lines, the firstsurface and the second surface being faced each other; and a pluralityof third electrode plugs positioned at intersections of the firstelectrode lines and the second electrode lines and connecting theresistive memory element pattern to one of the first electrode lines andthe second electrode lines.

Further embodiments of the present invention may provide stackedresistive memory arrays including: a plurality level of electrode linesconfigured to be insulated from adjacent levels of electrode lines by aninsulating layer; a plurality of resistive memory element patternsdisposed between the insulating layer and the respective level ofelectrode lines; and a plurality of electrode plugs passing through theinsulating layer corresponding to intersecting points of adjacent levelsof the electrode lines, and connecting respective electrode line and theresistive memory element pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application illustrate embodiment(s) of the invention. Inthe drawings:

FIG. 1 is a sectional view of a conventional resistive memory cell;

FIG. 2A is an energy diagram of a metal and a transition metal oxide ina set state and a reset state of a resistive memory cell according tosome embodiments of the present invention;

FIG. 2B is a current-voltage curve illustrating a switching mechanismbetween a set state and a reset state of a resistive memory cellaccording to some embodiments of the present invention;

FIG. 3 is a current-voltage curve of a resistive memory cell in avoltage-switching mode according to further embodiments of the presentinvention;

FIG. 4A is a schematic perspective view of a resistive memory cellaccording to additional embodiments of the present invention;

FIGS. 4B and 4C are schematic sectional views taken along lines I-I andII-II in FIG. 4A, respectively;

FIG. 5A is a graph of a current distribution with respect to two statesin the conventional resistive memory cell illustrated in FIG. 1;

FIG. 5B is a graph of a current distribution with respect to two statesin the resistive memory cell according to some embodiments of thepresent invention;

FIGS. 6 to 9 are sectional views taken along line I-I, showing variousmodifications of the resistive memory cells of FIGS. 4A-4C;

FIG. 10A is a perspective view of a resistive memory cell arrayaccording to some embodiments of the present invention;

FIG. 10B is an equivalent circuit diagram of the resistive memory cellarray illustrated in FIG. 10A;

FIG. 10C is a perspective view of a resistive memory cell of theresistive memory cell array illustrated in FIG. 10A;

FIGS. 11A and 11B are sectional views of the resistive memory cell arrayof FIG. 10A, taken along a direction of a second electrode and adirection of a conductive line, respectively;

FIG. 12 is an equivalent circuit diagram of a resistive memory cellarray including diodes according to further embodiments of the presentinvention;

FIG. 13 is a perspective view of a multi-level resistive memory cellarray according to additional embodiments of the present invention;

FIG. 14 is a perspective view of a multi-layer resistive memory cellarray according to further embodiments of the present invention;

FIG. 15A is an equivalent circuit diagram of a resistive memory cellarray according to yet further embodiments of the present invention;

FIG. 15B is a sectional view of two resistive memory cells, taken alonga direction perpendicular to a word line in the resistive memory cellarray of FIG. 15A;

FIG. 16 is a current-voltage curve illustrating a switchingcharacteristic in a resistive memory cell according to additionalembodiments of the present invention; and

FIG. 17 is a graph of a reset current in the conventional memory cell ofFIG. 1 and in resistive memory cells according to some embodiments ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. Like numbers refer to like elements throughout.As used herein the term “and/or” includes any and all combinations ofone or more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments and is not intended to be limiting of the invention. As usedherein, the singular forms “a”, “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “includes”and/or “including,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers refer to like elementsthroughout the specification.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in the figures is turned over, elements describedas being on the “lower” side of other elements would then be oriented on“upper” sides of the other elements. The exemplary term “lower”, cantherefore, encompasses both an orientation of “lower” and “upper,”depending of the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The exemplary terms “below” or “beneath” can, therefore,encompass both an orientation of above and below.

Embodiments of the present invention are described herein with referenceto cross-section illustrations that are schematic illustrations ofidealized embodiments of the present invention. As such, variations fromthe shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,embodiments of the present invention should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an etched region illustrated or described asa rectangle will, typically, have rounded or curved features. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the precise shape of a region of adevice and are not intended to limit the scope of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein. It will also be appreciated by those ofskill in the art that references to a structure or feature that isdisposed “adjacent” another feature may have portions that overlap orunderlie the adjacent feature, although other materials may be used.

Operation Characteristic of a Magneto-Resistive Memory Cell

Operation characteristics of magneto-resistive (hereinafter referred toas “resistive” or “magneto-resistive”) memory cells will be firstdescribed. A resistive memory cell may include a resistive memoryelement thin film disposed between two electrodes. It will be assumedfor the purpose of illustration that that two electrodes are formed ofiridium and the resistive memory element thin film is formed of nickeloxide layer that is a transition metal oxide.

When an asymmetric voltage is applied between two electrodes of theresistive memory cell, a filamentary current path may be formed, or afilamentary current path already formed may disappear. It is presumed,for the purposes of the following theoretical analysis, that thefilamentary current path is associated with defects in the resistivememory element thin film.

The defects of the resistive memory element thin film generate animpurity state in an energy band gap. For example, as illustrated inFIG. 2A, metal or oxygen vacancies generate a density of state near thevalence band or conduction band, while metallic states do the same justabove the electrode Fermi level.

When the metallic state is generated above the Fermi level of theresistive memory element thin film, the resistive memory cell has a lowresistance state (e.g., a set state). On the contrary, when the metallicstate disappears, the resistive memory cell becomes a high resistancestate (e.g., a reset state). To switch between the set state and thereset state, different voltages are applied to the two electrodes of theresistive memory cell. A reset voltage for the reset state is lower thana set voltage for the set state. For example, the set voltage may be1.5-2.5 times the reset voltage.

As illustrated in FIG. 2B, when switching from the high resistance stateto the low resistance state or vice versa, a clockwise orcounterclockwise I-V loop (current-voltage loop) is generated. A current(a set current) flow due to a voltage applied in the low resistancestate (the set state) decreases. It is because a vacant metallic stateis filled with injected charges by an increased bias voltage and thusthe vacant metallic state above the Fermi level gradually disappears inthe metallic filament. On the contrary, a current (a reset current) flowdue to a voltage applied in the high resistance state (the reset state)increases. It is because a metallic state increases due to discharge ofpreviously stored charges in the metallic detect state and aconductivity also increases in a vacant metallic state due to a heatingand percolation effect.

The switching between the set state and the reset state may take placeindependent of polarity of an applied voltage. Because the set voltageis higher than the reset voltage and the reset current is higher thanthe set current, the resistive memory element thin film can beprogrammed into either the set state or the reset state from anyprevious state by choosing proper pulse voltage and current, forexample, by applying a voltage lower than the reset voltage. Cellresistance can be read using voltage pulse less than the reset voltagewithout affecting the stored data.

FIG. 3 is an I-V curve illustrating a switching characteristic of aresistive memory cell having a resistive memory element thin film formedof a nickel oxide layer according to some embodiments of the presentinvention, In FIG. 3, a horizontal axis represents a voltage (V) appliedbetween a first electrode and a second electrode, and a vertical axisrepresents a current (mA) flowing through the nickel oxide layer.

The two electrodes of the resistive memory cell are formed of an iridiumlayer having a thickness of 500 Å. The nickel oxide layer has athickness of 200 Å. In addition, the nickel oxide layer is formed byalternately and repeatedly performing a first operation of forming anickel layer having a thickness of 10 Å using a sputtering technique anda second operation of oxidizing the nickel layer using an oxygen plasmatreatment. The second operation, that is, the oxygen plasma treatment,is performed for 30 seconds using oxygen gas injected under theconditions of a radio frequency power of 20 W and a flow rate of 2 sccm(standard cubic centimeter per minute). The resistive memory cell has a0.3×0.7 μm² rectangular shape.

Referring to FIG. 3, when a voltage of about 0.5 V is applied betweenthe two electrodes, the nickel oxide layer is switched to the highresistance state, that is, the reset state. When a voltage of about 1.1V is applied between the two electrodes, the nickel oxide layer isswitched to the low resistance state, that is, the set state. A currentof about 0.5 mA is applied, while a voltage of more than 1.0 V isapplied between the two electrodes to change the nickel oxide layer tothe set state. The current is controlled to prevent the nickel oxidelayer from being damaged when a large current flows through the nickeloxide layer of the set state. As illustrated in FIG. 3, the I-V curvefor a nickel oxide layer according to some embodiments of the presentinvention is symmetrical with respect to a starting point of a voltageof 0.0V and a current of 0.0 mA.

The resistive memory cell operations described above with reference toFIGS. 2 and 3 may be similarly applied to various resistive memorycells, which will be described later.

Structure and Formation of a Magneto-Resistive Memory Cell

FIG. 4A is a schematic perspective view of a magneto-resistive memorycell 100 according to some embodiments of the present invention. FIG. 4Bis a schematic sectional view taken along line I-I in FIG. 4A, and FIG.4C is a schematic sectional view taken along line II-II in FIG. 4A.

Referring to FIG. 4A, the resistive memory cell 100 includes a firstelectrode 111, a resistive memory element thin film 113, and a secondelectrode 115. The first electrode 111 has a plug shape and extends in avertical direction (z-axis). The resistive memory element thin film 113and the second electrode 115 are horizontally disposed on the firstelectrode 111. The second electrode 115 extends along an x-axis, i.e.,the second electrode 115 exhibits a linear shape. Along a y-axis, aminimum width of the second electrode 115 is greater than a width(diameter) of the first electrode 111. This will be apparent fromreference to FIGS. 4B and 4C.

Referring to FIGS. 4B and 4C, the first electrode 111 has a plug shape.The first electrode 111 fills a contact hole 112 that is formed withinan insulating layer 109. The resistive memory element thin film 113 isdisposed on the first electrode 111 and the insulating layer 109, andthe second electrode 115 is disposed on the resistive memory elementthin film 113. Along the y-axis, a minimum width W2 of the secondelectrode 115 is greater than a width (diameter) D1 of the firstelectrode 111.

Although FIGS. 4B and 4C show that a width W3 of the resistive memoryelement thin film 113 (along the y-axis) is greater than the minimumwidth W2 of the second electrode 115, in some embodiments, the width W3may be identical to the minimum width W2. As indicated by a dotted linein FIGS. 4A and 4B, along the x-axis, the second electrode 115 may havea minimum width W4. The second electrode 115 has a rectangular shapewith the width W4 along the x-axis and the width W2 along the y-axis. Inthe illustrated embodiments, because the minimum width W2 of the secondelectrode 115 is greater than the diameter D1 of the first electrode111, an overlapping area between the first electrode 111 and theresistive memory element thin film 113 is smaller than an overlappingarea between the second electrode 115 and the resistive memory elementthin film 113. The second electrode 115 can have any of a variety ofshapes, and the resistive memory element thin film 113 and the secondelectrode 115 can have the same shape.

In the specification, when relatively comparing the widths of the firstelectrode, the second electrode, and the resistive memory element thinfilm, the respective widths are measured in a same direction. In theabove embodiment, the width D1 of the first electrode 111, the width W2of the second electrode 115, and the width W3 of the resistive memoryelement thin film 113 are all measured in y-direction.

According to some embodiments of the present invention, because one(e.g., the first electrode 111) of the two electrodes has a plug shape,the overlapping area between the first electrode plug 111 and theresistive memory element thin film 113 can be smaller than theoverlapping area between the bottom electrode 22 and the CMR layer 24 ofFIG. 1. That is, a switching region 113 s where the resistance changesin operation is reduced much more than the conventional switching regionof FIG. 1. This switching region in the resistive memory element thinfilm 113 is shaded in FIGS. 4B and 4C. Compared with the prior art, theswitching operation characteristic of a device according to someembodiments of the present invention may be enhanced, which will bedescribed later in more detail. That is, in the repetitive switchingmechanisms, there may be very low resistance variation in the lowresistance state (the set state). Also, there is may be very lowresistance variation in the high resistance state (the reset state).Thus, even after many switching events, the set resistance in the lowresistance state and the reset resistance in the high resistance statemay be maintained substantially constant.

In a resistive memory cell according to some embodiments of the presentinvention, the first electrode plug 111 and the second electrode 115 maybe formed of material selected from the group consisting of iridium,platinum, ruthenium, polycrystalline silicon, tungsten (W), titaniumnitride (TiN), titanium aluminum nitride (TiAlN), and a combinationthereof.

A method of fabricating the resistive memory cell illustrated in FIGS.4A to 4C will now be described. An insulating layer 109 is patterned toform a contact hole 112. A conductive material for a first electrode isdeposited in the contact hole 112. Then, a planarization process, suchas a chemical mechanical polishing (CMP) or an etch-back, is performedto form a first electrode plug 111 in the contact hole 112. A resistivememory element thin film 113, such as a metal oxide, is formed on thefirst electrode plug 111 and the insulating layer 109. A conductivematerial for a second electrode is formed on the resistive memoryelement thin film 113. The conductive material for the second electrodeis patterned in a predetermined shape to form the second electrode 115.During the patterning process for the second electrode, the resistivememory element thin film 113 can also be patterned. In this case, theresistive memory element thin film 113 and the second electrode 115 mayhave substantially the same shape.

An improved resistance distribution characteristic can be seen fromFIGS. 5A and 5B. FIG. 5A is a graph of a current distribution withrespect to two states in the conventional resistive memory cellillustrated in FIG. 1, and FIG. 5B is a graph of a current distributionwith respect to two states in a resistive memory cell according to someembodiments of the present invention. The resistance distribution can bedetermined from the current distribution and the applied voltage ofFIGS. 5A and 5B. The resistance distribution exhibits similarcharacteristics to those of the current distribution.

For the conventional resistive memory cell configuration of FIG. 1, aresistive memory cell having a 1 μm×1 μm rectangular shape wasfabricated. Two electrodes were formed of iridium and a resistive memoryelement thin film was formed of a nickel oxide (NiO₂) with a thicknessof 200 angstroms.

For the resistive memory cell according to some embodiments of thepresent invention, a tungsten bottom electrode plug with a diameter of0.15 μm was formed, and a resistive memory element thin film was formedof a nickel oxide (NiO₂) with a thickness of 200 angstroms. A topelectrode with a diameter of 0.5 μm was formed of iridium, with a roundshape.

For switching to the reset state, a reset voltage of 0.8 V was appliedbetween the first electrode and the second electrode for 1 millisecond.For switching to the set state, a set voltage of 1.5 V was appliedbetween the first electrode and the second electrode for 1 millisecond.A current limit of about 0.5 mA was maintained while the set voltage wasapplied. The current in the set state and the reset state was measuredwhen a voltage of 0.2 V was applied between the two electrodes.

In FIGS. 5A and 5B, a horizontal axis represents the number ofoperations for the resistive memory cell and a vertical axis representsa current distribution measured in the set state and the reset state. InFIGS. 5A and 5B, an upper side represents the current distribution inthe set state and a lower side represents the current distribution inthe reset state.

As can be seen from FIGS. 5A and 5B, the resistive memory cell accordingto the present invention exhibits good switching operationcharacteristics compared with the conventional resistive memory cell.Also, it can be seen from FIG. 5A that the conventional resistive memorycell has a large current variation in the state and the reset state.Therefore, a sensing margin for discriminating the reset state and theset state may be very small.

However, it can be seen from FIG. 5B that the resistive memory cellaccording to some embodiments of the present invention has very lowcurrent variation in the reset state and the reset state. Therefore, asensing margin for discriminating the reset state and the set state maybe relatively large. According to some embodiments of the presentinvention, the reset state and the set state may be clearlydiscriminated, and a current difference between the two states may bevery large. This discrimination may be maintained even after a largenumber of switching operations.

In addition, the overlapping area between the first electrode and theresistive memory element thin film is reduced and thus leakage currentmay be reduced. If the overlapping area is small, boundaries betweengrains of the resistive memory element thin film may be reduced andtherefore leakage current via the grain boundaries may be reduced.

Further, by appropriately controlling a composition ratio of theresistive memory element thin film, the resistive memory cell may bedriven at a low operating voltage or low operating current. Theinventors have discovered that the set voltage and the reset voltage maybe influenced by oxygen content of a resistive memory element thin filmformed of a transition metal oxide.

For the low voltage or current driving, it is preferable that the oxygencomposition ratio of the transition metal oxide be smaller than theoxygen composition ratio of the stable state. In other words, it ispreferable that the transition metal oxide has a relatively largetransition metal content compared with its stable state. In a transitionmetal oxide, expressed as MO_(x), when the metal “M” is nickel (Ni),cobalt (Co), Zinc (Zn), or copper (Cu), “x,” composition ratio of oxygenatoms, may have a range from 0.5 to 0.99 (0.5≦x≦0.99). When the metal“M” is hafnium (Hf), zirconium (Zr), titanium (Ti), or chromium (Cr),“x” may have a range from 1.0 to 1.98 (1.0≦x≦1.98). When the metal “M”is iron (Fe), “x” may have a range from 0.75 to 1.485. When the metal“M” is niobium (Nb), “x” may have a range from 1.25 to 2.475.

Using various methods, the transition metal oxide can be formed to havethe above-described composition ratios of oxygen atoms. For example, thetransition metal oxide can be formed by alternately and repeatedlyperforming an operation of forming a transition metal layer and anoperation of oxidizing the transition metal layer using an oxygen plasmatreatment. The transition metal layer can be formed using a sputteringtechnique. The oxygen plasma treatment can be performed in-situ. In someembodiments, the transition metal oxide layer can be formed using O₂reactive sputtering technique, a chemical vapor deposition (CVD)technique, or an atomic layer deposition (ALD) technique.

FIGS. 6 to 9 are sectional views showing resistive memory cellsaccording to further embodiments of the present invention, which may beviewed as modifications of the structure shown in FIGS. 4A-4C. Theresistive memory cells of FIGS. 6 to 9 may have characteristics similarto those of the resistive memory cell described above with reference toFIGS. 4A-4C.

Referring to FIG. 6, insulating spacers 119 are formed on sidewalls of acontact hole 112. Accordingly, a diameter D2 of a first electrode plug111 (and, accordingly, of a portion 113 s of a resistive memory elementthin film 113 contacting the plug 111) in the resistive memory cell ofFIG. 6 may be smaller than the diameter D1 of the first electrode plug111 in the resistive memory cell of FIG. 4B by two times the width ofthe insulating spacer 119. Accordingly, the switching operationcharacteristic of the resistive memory cell may be further improved.Prior to depositing a conductive material for the first electrode plugafter forming the contact hole 112, the insulating spacers 119 of FIG. 6can be formed by depositing an insulating material and performing anetch-back process on the insulating material. The insulating spacers 119can be formed of, for example, silicon nitride.

In further embodiments, a resistive memory element thin film 113′ canextend into the contact hole as shown in FIGS. 7 to 9. For this, acontact hole 112 is partially filled with a first electrode plug 111′.The forming of the first electrode plug 111″ recessed downward from thetop of the insulating layer 109 may include forming a conductive layerfor the first electrode and sequentially performing a planarizationprocess and an etch-back process, or performing an etch-back process. Aportion of the contact hole 112 is filled with the first electrode plug111″ and a portion of the contact hole 112 is filled with the resistivememory element thin film 113′.

The resistive memory cell of FIG. 7 includes two insulating spacers. Oneis a lower insulating spacer 119 formed on sidewalls of the contact hole112, like the resistive memory cell illustrated in FIG. 6. The other isan upper insulating spacer 119′ formed on sidewalls of a narrowercontact hole 112′ defined by the lower insulating spacer 119.Accordingly, the resistive memory cell of FIG. 7 may have a relativelysmaller overlapping area between the first electrode 111′ and theresistive memory element thin film 113′ than the resistive memory cellof FIG. 6.

Further embodiments of the present invention include variousmodifications of the resistive memory cells described above. In FIG. 8,a resistive memory cell according to some embodiments uses a recessedfirst electrode plug 111′″ and an upper insulating spacer 119″ in acontact hole 112. In FIG. 9, a resistive memory cell according tofurther embodiments uses a recessed first electrode plug 111″ and alower insulating spacer 119′″.

A first electrode plug may be formed from multiple conductive layers.For example, after forming a recessed electrode plug as exemplarilyillustrated in FIGS. 7-9, another electrode material may be depositedthereon. Then, a planarization process may be performed to form anotherelectrode plug. If a conductive pattern to be connected to the recessedelectrode plug is polycrystalline silicon doped with impurities ofdifferent conductivity type from the recessed electrode plug, a diodemay be formed. A resistive memory pattern can be connected to the diode.Functions of such a diode will be described later. Resistive memorycells in which additional lower and upper insulating spacers arecombined in the multi-layered electrode plug structure can be provided.

A Magneto-Resistive Memory Array

In some embodiments of the present invention, various kinds of unitresistive memory cells, such as those illustrated in FIGS. 4A-4C and6-9, may be arranged in a resistive memory array. A resistive memoryarray according to some embodiments of the present invention may be across point memory array that does not require select transistors foraccess to respective resistive memory cells. A resistive memory arrayaccording to further embodiments of the present invention can includerespective select transistors for access to respective resistive memorycells. Such a resistive memory array with the select transistors can beformed using a CMOS process.

A cross point memory array according to some embodiments of the presentinvention will now be described. When a second electrode (or a topelectrode) of a resistive memory cell in the cross point memory arrayhas a linear shape, the second electrode may serve as a word line. Afirst electrode (or a bottom electrode) may have a plug shape and afirst electrode plug of the same column (or a row) may be connected tothe same conductive line, which may act as a bit line. Conductive linesconnecting the first electrode plugs can act as word lines and theline-shaped second electrodes can act as bit lines. As described above,because the resistive memory cell switches between two resistance statesregardless of the polarities of the voltage applied between the twoelectrodes, which line serves as a word line and a bit line may dependon which electrode a relatively high voltage is applied to.

FIG. 10A is a perspective view of a resistive memory array according tosome embodiments of the present invention. FIG. 10B is an equivalentcircuit diagram of the resistive memory array illustrated in FIG. 10A.FIG. 10C is a perspective view of a resistive memory cell of theresistive memory array illustrated in FIG. 10A. A plurality of secondelectrodes (top electrodes) 207 is arranged in parallel in a rowdirection (x-axis). A plurality of conductive lines 201 is arranged inparallel in a column direction (y-axis). The second electrodes 207 andthe conductive lines 201 intersect at a plurality of points. In someembodiments, the second electrodes 207 may be word lines and theconductive lines 201 may be bit lines. In other embodiments, the secondelectrodes 207 may be bit lines and the conductive lines 201 may be wordlines.

A plurality of first electrodes (bottom electrodes) 203 are disposed atthe intersecting points of the second electrodes 207 and the conductivelines 201. The first electrodes 203 in a given column are commonlyconnected to one of the conductive lines 201. A resistive memory elementthin film 205 is disposed between the first electrodes 203 and thesecond electrodes 207. The resistive memory element thin film 205 canhave various shapes. In the illustrated embodiments, the resistivememory element thin film 205 covers the memory cell array. In someembodiments, the resistive memory element thin film 205 may be brokeninto linear regions having, for example, substantially same shape as thesecond electrodes 207.

A diameter of the first electrode 203 is smaller than a width of theconductive line 201 and a width of the second electrode 207. A specificconductive line 201 and a specific second electrode 207 may be selectedby a row/column decoder, such that the resistive memory cell at thecorresponding intersecting point is selected. A sense amplifier isconnected to the bit line and reads data stored in the selectedresistive memory cell. Any of a number of different row/column decodingand sense amplifier operations known in the art may be used.

Operations for forming the conductive lines 201 will now be describedwith reference to FIGS. 11A and 11B. FIGS. 11A and 11B are sectionalviews of the resistive memory array illustrated in FIG. 10A, taken alongthe x-direction and the y-direction, respectively. Formation of theconductive lines 201 may include forming a conductive material (e.g., apolycrystalline silicon doped with impurities) on a substrate 200, andpatterning the conductive material. A mask defining the outline of theconductive lines may be formed on the substrate 200, and used for ionimplantation. An insulating layer 202 is formed and patterned to formcontact holes 204 for formation of the first electrodes. A conductivematerial is deposited to fill the contact holes 204, and a planarizationprocess is performed to form the first electrodes 203 within the contactholes 204. A transition metal oxide layer 205 is formed, and aconductive material layer is formed on metal oxide layer 205. Theconductive material is patterned to form the second electrodes 207.

By selecting a particular conductive line 201 and a particular secondelectrode 207, a resistive memory cell disposed at the intersectingpoint of the particular conductive line 201 and the particular secondelectrode 207 is selected. In order to reduce leakage current directedtoward resistive memory cells other than the selected resistive memorycell, the resistive memory array can further include diodes 209, asillustrated in FIG. 12. The diodes 209 are disposed between the firstelectrode 203 and the conductive line 201. The diodes 209 may be formedby forming the conductive lines 201 using doped polysilicon orpolysilicon with implanted impurities, depositing an insulating layer,forming contact holes defining the first electrodes, and implantingimpurities having a conductivity type opposite to the conductivity ofthe conductive lines 201. Schottky barrier type contacts may also beformed at interfaces between the conductive lines 201 and the firstelectrodes 203.

FIG. 13 is a partially cut-away perspective view of a multi-levelresistive memory array according to additional embodiments of thepresent invention. Unlike the resistive memory array of FIG. 10, theresistive memory array of FIG. 13 includes unit memory cells arranged invertical and horizontal planes. The resistive memory array of a certainlevel (along the z-axis) is identical to the resistive memory arraydescribed above with reference to FIG. 10, Vertically adjacent electrodelines are perpendicular to each other, and a plug-shaped electrode and aresistive memory element thin film are disposed at an intersection ofthe two vertically adjacent electrode lines. The plug-shaped electrodeconnects a conductive line of a lower level and a resistive memoryelement thin film disposed under an electrode line of an upper level.

In the multi-level resistive memory array according to such embodiments,the conductive lines of the lowermost level and the electrode lines ofthe uppermost level can act as word lines and bit lines under a firstvoltage condition. An electrode line disposed between the uppermostlevel and the lowermost level may act as a word line and bit line undera second voltage condition.

The multi-level resistive memory array will be described below in moredetail with reference to FIG. 13. Referring to FIG. 13, 3-layeredstructure is illustrated. A conductive line 301 of the lowermost levelcorresponds to the conductive line 201 of FIG. 10A and extends in a rowdirection (x-direction). An electrode line 401 of a second level extendsin a column direction (y-direction) and a resistive memory element thinfilm line 405 is disposed on the bottom surface of the electrode line401. The electrode line 401 of the second level and the conductive line301 of the first level are perpendicular to each other, and an electrodeplug 303 is disposed at their intersection. An electrode line 501 of athird level extends in the row direction (x-direction) and isperpendicular to the electrode line 401 of the second line. An electrodeplug 403 is disposed at the intersection of the electrode line 501 ofthe third level and the electrode line 401 of the second level. Aresistive memory element thin film line 505 is disposed on the bottomsurface of the electrode line 401 of the third level.

The electrode line 401 may be a word line, the electrode line 401 may bea bit line and the electrode line 501 may be word line. First ends ofthe electrode line and the conductive line may be formed on thesubstrate through a contact plug or the like so as to form a currentpath, and may be connected to a drain of a transistor having its sourcegrounded. Second ends of the electrode line and the conductive line maybe connected to a row/column decoder.

According to some embodiments of the present invention, a multi-levelresistive memory array can array resistive memory cells vertically aswell as horizontally. Therefore, more highly integrated memory devicesmay be implemented. In the illustrated embodiments, the resistive memoryelement takes the form of parallel lines having the same shape as theelectrode lines. In some embodiments, the resistive memory element canalso cover the resistive memory cell region, as illustrated in FIG. 14.

FIG. 15A is an equivalent circuit diagram of a resistive memory cellarray with select transistors according to further embodiments of thepresent invention. FIG. 15B is a sectional view of two such resistivememory cells. Referring to FIG. 15A, one terminal (e.g., a bottomelectrode) of each of the resistive memory cells 305 is connected to adrain of a select transistor 307, and the other terminal (e.g., a topelectrode) is connected to a bit line 303. A gate of each of the selecttransistors is extended to form a word line 301. A source of the selecttransistor is connected to a ground voltage. When a bias voltage higherthan a threshold voltage is applied to a gate of the select transistor307 and an appropriate operating voltage is applied to the bit line 303,the resistive memory cell 305 is selected. Then, a read operation or aswitching operation is performed on the selected resistive memory cellresponsive to the voltage applied to the bit line 303.

Referring to FIG. 15B, a device isolation layer 403 is provided in apredetermined region of a semiconductor substrate 400, defining anactive region. The device isolation region 403 can be formed by awell-known isolation process, such as a shallow trench isolation (STI)process. Spaced-apart first and second drain regions 409Da and 409Db areformed in the active region. A common source region 409S is formedbetween the first and second drain regions 409Da and 409Db. A first gateelectrode 407 a is disposed on the active region between the commonsource region 409S and the first drain region 409Da. A second gateelectrode 407 b is disposed on the active region between the commonsource region 409S and the second drain region 409Db. The first andsecond gate electrodes 407 a and 407 b extend perpendicular to thesection plane and serve as first and second word lines, respectively.The first and second gate electrodes 407 a and 409 b are insulated fromthe active region by the gate insulating layer 405. The first gate 407a, the common source region 409S, and the first drain region 409Da forma first select transistor, and the second gate 407 b, the common sourceregion 409S, and the second drain region 409Db form a second selecttransistor. These select transistors can be fabricated using known CMOSprocesses. The gate electrode can be formed by depositing and patterninga conductive material, and the source and drain regions can be formed byimplanting impurity ions.

The select transistors and the device isolation layers 403 are coveredwith a first insulating layer 415. The first insulating layer 415 maybe, for example, a silicon oxide layer, a silicon nitride layer, or acombination layer thereof. The common source region 409S is electricallyconnected through the source contact plug 413S to the common source line417S formed on the first insulating layer 415. The common source line417S can be disposed parallel to the gates 407 a and 407 b. The firstdrain region 409Da is electrically connected to the first drain contact417Da through a first drain contact plug 413Da penetrating the firstinsulating layer 415. The second drain region 409Db is electricallyconnected to the second drain contact 417Db through a second draincontact plug 413Db penetrating the first insulating layer 415. Thecommon source line 417S, the drain contacts 417Da and 417Db, and thecontact plugs 413S, 413Da and 413Db can be formed by patterning aninsulating layer, depositing a conductive layer, and patterning thedeposited conductive layer.

A second insulating layer 419 is disposed on the first insulating layer415. The second insulating layer may be, for example, a silicon oxidelayer, a silicon nitride layer, or a combination layer thereof. A firstbottom electrode plug 421 a penetrates the second insulating layer 419and is electrically connected to the first drain contact 417Da. A secondbottom electrode plug 421 b is electrically connected to the seconddrain contact 417Db. The resistive memory element pattern 423 covers thesecond insulating layer 419 and the first and second bottom electrodeplugs 421 a and 421 b. A top electrode line 425 perpendicular to thegates 407 a and 407 b is disposed on the resistive memory elementpattern 423. A resistive memory cell is formed at the intersection ofthe first bottom electrode plug 421 a and the top electrode line 425.Likewise, a resistive memory cell is formed at the intersection of thesecond bottom electrode plug 421 b and the top electrode line 425. Thebottom electrode plug, the resistive memory element pattern, and the topelectrode line can be formed using the above-described methods.

FIG. 16 illustrates an I-V curve of a switching mechanism of theresistive memory cell according to some embodiment of the presentinvention. In FIG. 16, a horizontal axis represents a voltage (V)applied for the set and reset operations, and a vertical axis representsa current (mA) with respect to the applied voltage. Referring to FIG.16, it can be seen that a resistive memory cell structure according tosome embodiments of the present invention exhibits a low set current andlow reset current of less than 1 mA. As described above, it can beactually confirmed that the set current is lower than the reset current.

It can be seen from FIG. 17 that a resistive memory cell structureaccording to some embodiments of the present invention may exhibit alower operating current than a conventional resistive memory cellstructure. FIG. 17 is a graph illustrating a distribution of a resetcurrent (mA) in the conventional memory cell of FIG. 1 and the resistivememory cells according to an embodiment of the present invention. Inthis measurement, for the resistive memory of the present invention, atungsten bottom electrode with a diameter of 0.15 μm was formed, and aniridium top electrode with a diameter of 0.5 μm was formed. A resistivememory cell having the structure illustrated in FIG. 1 and having a 0.3μm×0.7 μm rectangular shape was formed. The resistive memory elementthin film thereof was formed of a nickel oxide with a thickness of 200angstroms. Referring to FIG. 17, it can be seen that a resistive memorycell according to some embodiments of the present invention may have asignificantly lower reset current than such a conventional resistivememory cell.

According to some embodiments of the present invention, one of the twoelectrodes in the resistive memory cell has a plug shape. Accordingly,the switching region thereof may be restricted by the overlapped areabetween the resistive memory element thin film and the electrode plug.In such device, even after repeated switching operations, there may belittle or no variation in the resistance distributions of the set stateand the reset state, which may improve the resistive dispersioncharacteristic and sensing margin. Consequently, reliable and robustmemory devices may be obtained. In addition, the overlapping areabetween the electrode and the resistive memory element thin film may bereduced and leakage current through the grain boundary of the resistivememory element thin film may be reduced. Furthermore, operating currentmay be reduced and stabilized.

Because the electrode material used for the resistive memory cell may bedifficult to etch, its sidewalls may be inclined after etching.Accordingly, there is a strong possibility of electrical short betweenthe adjacent electrodes. If the electrodes are spaced far away from eachother so as to prevent the electrical short therebetween, highintegration required by the memory devices cannot be achieved. However,according to the present invention, one of the two electrodes has a plugshape and, therefore, dry etching of the plug shaped contact may beavoided. Therefore, the risk of forming an electrical short betweenadjacent electrodes may be reduced, which may allow reduction of thedistance between the adjacent top electrodes compared with conventionaldevices. According to further aspects of the present invention,resistive memory cells can be arrayed vertically and horizontally,allowing the formation of highly integrated memory devices.

Many alterations and modifications may be made by those having ordinaryskill in the art, given the benefit of the present disclosure, withoutdeparting from the spirit and scope of the invention. Therefore, it mustbe understood that the illustrated embodiments have been set forth onlyfor the purposes of example, and that it should not be taken as limitingthe invention as defined by the following claims.

1. A memory cell comprising: a plug-type first electrode in a substrate; a transition metal oxide resistive memory element film disposed on the first electrode; and a second electrode disposed on the resistive memory element film opposite the first electrode, the second electrode having an area of overlap with the transition metal oxide resistive memory element film that is greater than an area of overlap of the first electrode and the transition metal oxide resistive memory element film.
 2. The memory cell of claim 1, wherein the area of overlap of the first electrode is substantially circular and has a diameter less than a minimum dimension of the area of overlap of the second electrode.
 3. The memory cell of claim 1, wherein the transition metal oxide resistive memory element film comprises a layer pattern having a minimum planar dimension that is less than a minimum planar dimension of the second electrode.
 4. The memory cell of claim 1, wherein the first electrode is disposed in an insulating layer and an insulating spacer is disposed between the first electrode and the insulating layer.
 5. The memory cell of claim 4, wherein the first electrode partially fills a contact hole in the insulating layer, and wherein the transition metal oxide resistive memory element film extends into the contact hole to contact the first electrode.
 6. The memory cell of claim 1, further comprising a conductive line electrically connected to the plug-type first electrode and disposed under the plug-type first electrode, wherein the conductive line is transverse to the second electrode.
 7. The memory cell of claim 1, wherein the transition metal oxide resistive memory element film comprises a transition metal oxide with the formula MO_(x), wherein M is nickel (Ni), cobalt (Co), zinc (Zn) or copper (Cu), and wherein x is in a range from about 0.5 to about 0.99.
 8. The memory cell of claim 1, wherein the transition metal oxide resistive memory element film comprises a transition metal oxide with the formula MO_(x), wherein M is hafnium (Hf), zirconium (Zr), titanium (Ti) or chromium (Cr), and wherein x is in a range from about 1.0 to about 1.98.
 9. The memory cell of claim 1, wherein the transition metal oxide resistive memory element film comprises a transition metal with the formula MO_(x), wherein M is iron (Fe) and wherein x is in a range from about 0.75 to about 1.485.
 10. The memory cell of claim 1, wherein the transition metal oxide resistive memory element film comprises a transition metal oxide with the formula MO_(x), wherein M is niobium (Nb) and wherein x is in a range from about 1.25 to about 2.475.
 11. The memory cell of claim 1, wherein the first electrode comprises iridium (Ir), platinum (Pt), ruthenium (Ru), polycrystalline silicon, tungsten (W), titanium nitride (TiN) and/or titanium aluminum nitride (TiAlN).
 12. The memory cell of claim 1, wherein the first electrode comprises tungsten, wherein the second electrode comprises iridium and wherein the transition metal oxide resistive memory element film comprises nickel oxide. 